Chemical-mechanical polishing (CMP) is used extensively as a planarizing technique in the manufacture of VLSI integrated circuits. It has potential for planarizing a variety of materials in IC processing but is used most widely for planarizing metallizied layers and interlevel dielectrics on semiconductor wafers, and for planarizing substrates for shallow trench isolation.
In shallow trench isolation (STI), for example, large areas of field oxide must be polished to produce a planar starting wafer. Achieving acceptable planarization across the full diameter of a wafer using traditional etching processes has been largely unsuccessful. However, using conventional CMP, where the wafer is polished using a mechanical polishing wheel and a slurry of chemical etchant, unwanted oxide material is removed with a high degree of planarity.
Similarly, in multilevel metallization processes, each level in the multilevel structure contributes to irregular topography. Planarizing interlevel dielectric layers, as the process proceeds, is often now favored in many state-of-the-art IC fabrication processes. High levels of planarity in the metal layers is a common objective, and this is promoted by using plug interlevel connections. A preferred approach to plug formation is to blanket deposit a thick metal layer, comprising, for example W, Ti, TiN, on the interlevel dielectric and into interlevel windows, and then removing the excess metal using CMP. CMP may also be used for polishing an oxide layers, such as SiO2, Ta2O5 or W2O5 or to polish nitride layers such as Si3N4, TaN, TiN.
There are, however, several deficiencies in conventional polishing pad materials. Various types of materials, such as polyurethane, polycarbonate, nylon, polyureas, felt, or polyester, have poor inherent polishing ability, and hence are not used as polishing pads in their virgin state. In certain instances, mechanical or chemical texturing may transform these materials, thereby rendering them useful in polishing. Another consideration important to preventing uneven polishing of wafers is the choice and longevity of the backing film used for attaching the polishing pad to the platen of the polishing table. The backing film cushions the wafer during polishing and compensates for thickness variations in the wafer or backing plate. Still another consideration is the adhesive used to attach the polishing pad to the platen.
The slurries used in chemical mechanical polishing are thought to cause delamination of the polishing pad from the platen of the polishing table. Ensuing problems can range from unsatisfactory planarization of wafers producing poor quality wafers in the early stages of delamination, to total destruction of wafers and polishing equipment, when the delaminated polishing pad flies off a moving polishing table. Delamination is thought to occur when the adhesive used to fix the polishing pad to the platen of the polishing table is chemically attacked by the slurry. This, in turn, results in adhesive failure at the adhesive/platen interface, probably due to dissolution of the adhesive. The reduction in the numbers of sufficiently high quality semiconductor wafers produced because of delamination contributes significantly to the overall cost of producing integrated circuits.
One approach to reduce losses in production due to delamination is to use an adhesive that strongly couples the polishing pad to the platen. This approach is based on the notion that if the polishing pad is tightly coupled to the platen, then the polishing slurry will less readily gain ingress between the platen and the pad to cause delamination. One problem with this approach, however, is that it becomes extremely difficult to change polishing pads. Special equipment is generally required to facilitate peeling such pads off of the platen. Often residual adhesive is left on the platen surface, necessitating the use of organic solvents to clean adhesive off of the platen. These additional removal and cleaning steps add to the total time and cost of producing integrated circuits.
Accordingly, what is needed is an improved CMP pad capable of providing a highly planar wafer surface and having improved longevity during CMP, while not experiencing the above-mentioned problems.